1. Field of the Invention
The present invention relates to a peak value detecting circuit and, more particularly, to a peak value detecting circuit which handles signals of low levels.
2. Description of the Prior Art
Peak value detecting circuits are known to be used in various electronic devices. The peak value detecting circuit is a circuit that keeps monitoring the magnitude of an input signal voltage and maintains under a certain level the highest voltage of that input signal. FIG. 1 is a block diagram of a typical prior art peak value detecting circuit. As shown in FIG. 1, the peak value detecting circuit comprises a voltage comparing section 1, a peak voltage holding circuit 2, a holding voltage control circuit 3 and a signal output circuit 4.
In this prior art peak value detecting circuit, an externally input signal is applied to a compare input terminal of a comparator which constitutes the voltage comparing section 1. At the same time, the voltage held by the peak voltage holding circuit 2 is supplied to a reference input terminal of the comparator 5. The two input signals are compared in terms of level. If the externally input signal is greater than the reference voltage, the former signal is held as a new peak value by a peak holding capacitor Cp in the peak voltage holding circuit 2. In this manner, the peak voltage holding circuit holds the signal of the highest level that has been input so far.
The signal output circuit 4 forwards to the outside the peak voltage held by the peak voltage holding circuit 2. Acting as it does, the circuit 4 serves as a buffer arrangement with external circuits. The signal output circuit 4 may be implemented using a buffer amplifier 6 that performs impedance conversion. One disadvantage of the buffer amplifier 6 is that it can develop a DC offset. The DC offset can cause some undesirable effects. For example, when a peak value Vp held by the peak voltage holding circuit 2 is output to the outside via the buffer amplifier 6, a positive offset Ov shown in FIG. 2 (A) or a negative offset Ov depicted in FIG. 2 (B) appears unchecked in the output of the peak value detecting circuit. For this reason, the conventional peak value detecting circuit suffers irregularities in its input/output characteristic. The disadvantage is particularly pronounced when the level of the signal handled is low.